This invention is in the field of integrated circuits, and is more specifically directed to electrostatic discharge protection devices in modem integrated circuits.
Modern high-density integrated circuits are known to be vulnerable to damage from the electrostatic discharge (ESD) of a charged body (human or otherwise) that physically contacts the integrated circuit. ESD damage occurs when the amount of charge exceeds the capability of the conduction path through the integrated circuit. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting (e.g., in the metal-oxide-semiconductor, or MOS, context).
To avoid damage from ESD, modern integrated circuits incorporate ESD protection devices at each external terminal. ESD protection devices generally operate by providing a high capacity conduction path for the brief but massive ESD charge, safely conducting this energy away from other structures that are not capable of handling the event. In some cases, ESD protection is inherent to the particular terminal, as in the case of a power supply terminal which may provide an extremely large p-n junction that can absorb the ESD charge. Inputs and outputs, on the other hand, typically have a specific ESD protection device added in parallel with the functional terminal. The ideal ESD protection device turns on quickly in response to an ESD event, with large conduction capability, but remains off and presents no load during normal operation.
Examples of ESD protection devices are well known in the art. In the case of MOS technology, an early ESD protection device was provided by a parasitic thick-field oxide MOS transistor that was turned on by and conducted ESD current, as described in U.S. Pat. No. 4,692,781 and in U.S. Pat. No. 4,855,620, both assigned to Texas Instruments Incorporated and incorporated herein by this reference.
As the feature sizes of MOS integrated circuits became smaller, and with the advent of complementary MOS (CMOS) technology, the most popular ESD protection devices utilized a parasitic bipolar device to conduct the ESD current, triggered by way of a silicon-controlled-rectifier (SCR) structure. SCRs are very robust devices, as they can repeatedly conduct relatively large transient currents without being vulnerable to irreversible breakdown damage and the like. The CMOS parasitic SCR is formed by way of a p-type source/drain region serving as the SCR anode, an n-type source/drain region serving as the SCR cathode, and corresponding n-type and p-type wells serving as the bases of the parasitic p-n-p and n-p-n bipolar transistors. Examples of a CMOS parasitic SCR protection device is described in Rountree et al., “A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes”, 1988 EOS/ESD Symposium, pp. 201-205, and in U.S. Pat. No. 5,012,317 assigned to Texas Instruments Incorporated, both incorporated herein by this reference.
FIG. 1a illustrates, in cross-section, an example of this conventional CMOS parasitic SCR ESD protection device in an integrated circuit. In this example, the structure is formed at a surface of p-type substrate 10, which has n-well 12 formed at a surface. Isolation oxide structures 15, which in this case are field oxide structures formed by conventional LOCOS (local oxidation of silicon), define the active regions of the surface, at which n+ regions 14, 20, and p+ region 16 are formed by masked ion implant. In this arrangement, the anode of the protection device is region 16, which is connected to terminal 18, typically a bond pad for receiving an external connection of the integrated circuit when packaged. N+ region 14 is also formed in n-well 12 along with p+ region 16, and is connected to terminal 18 to ensure that the p-n junction between p+ region 16 and n-well 12 is not forward biased in normal operation. In some cases, for example at CMOS push-pull outputs, n+ region 14 may instead be tied to a power supply (Vcc) bus of the integrated circuit, rather than to terminal 18. The cathode of the structure is n+ region 20, which is connected to ground in the integrated circuit. In the ESD context, the integrated circuit is not biased to power supply voltages or system ground, and as such the ground connection to n+ region 20 is established by the connection of this region to one or more large doped regions in the integrated circuit, sufficiently large to serve as a sink for the charge received in an ESD event. In operation, as described in U.S. Pat. No. 5,012,317, a positive polarity ESD event received at terminal 18 and applied to regions 14, 16 will forward bias the p-n junction between p+ region 16 and n-well 12, and eventually cause the junction between n-well 12 and p substrate 10 to enter avalanche breakdown. Electrons generated by this avalanche breakdown provide the initial base current for the p-n-p device, and holes generated by this avalanche breakdown provide the initial base current for the n-p-n device. The parasitic p-n-p transistor formed by p+ region 16 (emitter), n-well 12 (base), and p substrate 10 (collector) will then turn on, providing base current to the parasitic lateral n-p-n transistor formed by n+ region 14 and n-well 12 (collector), p substrate 10 (base) and n+ region 20 (emitter). Likewise, the n-p-n device will turn on, providing base current to the p-n-p device. These two parasitic bipolar devices operate as an SCR, and safely conduct the current from the ESD event to the cathode (n+ region 20), preventing damage to functional circuitry connected to terminal 18.
By way of further background, several improvements and modifications have been made over the years to the CMOS SCR protection device design. The SCR breakdown voltage has been reduced by including an n-type source/drain diffusion straddling the well boundary, as described in U.S. Pat. No. 4,939,616, assigned to Texas Instruments Incorporated and incorporated herein by this reference. An example of this structure, commonly referred to as a low voltage SCR (LVSCR), is shown in FIG. 1b. The structure of FIG. 1b is constructed similarly to that of FIG. 1a, but includes an additional n+ region 22 that straddles the boundary of n-well 12. N+ region 22 is effectively resistively connected to terminal 18, with the resistance established by portions of n-well 12 near terminal 18. As described in U.S. Pat. No. 4,939,616, n+ region 22 in the structure of FIG. 1b assists the triggering of the SCR, because of the reduced avalanche breakdown voltage at the junction between relatively heavily doped n+ region 22 and p substrate 10, as compared with the breakdown voltage at the junction between lightly-doped n-well 12 and lightly-doped p substrate 10.
U.S. Pat. No. 5,465,189, assigned to Texas Instruments Incorporated and incorporated herein by this reference, describes a CMOS SCR (commonly referred as the “LVTSCR”) in which the n-type source/drain region straddling the well boundary is gated. An example of a structure according to this approach is shown, in cross-section, in FIG. 1c. In this example, n+ region 22 straddles the boundary of n-well 12 as in the case of FIG. 1b. Polysilicon electrode 26 is disposed between n+ region 22 and n+ region 20 (which is outside of n-well 12), overlying gate dielectric 24, thus forming an MOS transistor. Gate electrode 26 is connected to ground, either directly, as shown, or alternatively through a resistor, as described in U.S. Pat. No. 5,907,462. N+ region 20 is also connected to ground. As described in U.S. Pat. No. 5,465,189, this gated device effectively defines a desired low SCR trigger voltage.
U.S. Pat. No. 5,907,462, assigned to Texas Instruments Incorporated and incorporated herein by this reference, describes a CMOS SCR with a gated well diode. FIG. 1d illustrates an example of an SCR protection device of this type. The SCR portions of this structure within n-well 12 is similar to that of the example of FIG. 1a. Gate electrode 28 overlies gate dielectric 27, straddling the well boundary and overlapping onto field oxide structure 15. Gate electrode 28 is connected to ground, along with n+ region 20 outside of n-well 12, as shown. In operation, as described in U.S. Pat. No. 5,907,462, gate electrode 28 is the gate of a parasitic MOS device, having n-well 12 as its drain and n+ region 20 as its source, and which turns on in response to an ESD event to assist the triggering of the SCR.
In recent years, however, many modem high-performance integrated circuits have begun using devices other than SCRs for ESD protection. Gate-coupled nMOS devices have become popular, because the fast switching time of these devices provides improved performance according to the Charged Device Model (CDM), which models electrostatic discharge from a charged integrated circuit to ground. It has been observed that the switching times of parasitic SCRs are relatively slow, in modern advanced CMOS devices, because the gain of the parasitic bipolar devices is generally quite low. One cause of this low gain is the use of retrograde well ion implant profiles (i.e., increasing dopant concentration with depth into the semiconductor), which has the effect of blocking vertical conduction paths through the SCR. Another cause of low bipolar gain in SCR protection devices in advanced CMOS processes stems from shallow trench isolation (STI) structures, serving as isolation oxide structures in place of conventional LOCOS field oxide structures in modem CMOS processes. These STI structures block the lateral conduction path from anode to cathode, effectively decreasing the gain of the triggering parasitic bipolar transistor. For example, the current gain β of the parasitic bipolar transistors in prior LOCOS CMOS SCR protection devices typically ranges from about 10 to 30; in modern advanced CMOS processes, the parasitic bipolar typically has unity gain.
By way of further background, U.S. Pat. No. 6,081,002, assigned to Texas Instruments Incorporated and incorporated herein by this reference, describes an SCR-based ESD protection device for use in a CMOS technology using shallow trench isolation (STI) structures. FIG. 1e illustrates an example of a device according to this approach, in which STI structure 109 is disposed between n+ region 14 and p+ region 16 in n-well 12. P+ region 22 straddles the well boundary. Gate electrode 26 is disposed between n+ region 20 and region 22 and is biased to ground with n+ region 20, while gate electrode 30 is disposed between region 22 and p+ region 16, overlying a gate dielectric, and is connected to terminal 18. In operation responsive to an ESD event at terminal 18, the junction between n-well 12 and p+ region 22 will break down, triggering the SCR to safely conduct the ESD energy. Alternatively, as described in U.S. Pat. No. 6,081,002, region 22 may be doped n+, in which case the NMOS transistor gated by gate electrode 26 will break down by punchthrough between source and drain regions 20, 22 via p-substrate 10, also triggering the SCR. Further in the alternative, as described in U.S. Pat. No. 6,081,002, region 22 may be constructed as an adjacent pair of p+ and n+ regions, enabling both triggering mechanisms. Also as described in this Patent, gate electrode 30 defines an isolation transistor, eliminating the need for an STI structure at that location and thus avoiding the loss of bipolar gain that such an isolation structure would present. In addition to providing the parasitic MOS transistor function, gate electrodes 26 and 30 also serve to block the formation of silicide at the surface of p substrate 10 and n-well 12, respectively. The presence of silicide at these locations would result in the shorting of regions 16, 20, and 22, n-well 12 and p-substrate 10.
Another approach toward avoiding the gain degradation of STI structures involves an SCR structure in combination with a drain-extended nMOS (DENMOS) device, as described in Kunz et al., “5-V Tolerant Fail-safe ESD Solutions for 0.18 μm Logic CMOS Process”, ESD/EOS Symposium (Sep. 11, 2001), incorporated herein by this reference. An example of this structure is illustrated, in cross-section, in FIG. 1f. In this example, DENMOS transistor 9 is in parallel with SCR 11. Source region 31 of transistor 9 is connected to ground, while drain 14 is located within n-well 12, and is connected to terminal 18 at the anode of SCR 11, along with p+ region 16. P+ region 16 and n+ drain region 14 are separated from one another by shallow trench isolation STI structure 19. P+ region 16 is also located within n-well 12, as is a portion of n+ trigger region 22 in SCR 11. The cathode of SCR 11 is n+ region 20, which is biased to ground and disposed within p-type substrate 10. Each of heavily-doped regions 14, 16, 20, 22, 31 are clad with metal silicide film 28, as are other diffused regions within the same integrated circuit, for improved conductivity. In this structure of FIG. 1f, silicide formation is blocked by nitride structures 32 and polysilicon gate 34, formed by conventional photolithography and patterned etches. Gate 34 is the gate electrode of DENMOS transistor 9, and its nitride structures 32 are sidewall filaments. More specifically, the nitride structures 32 on either side of n+ region 28 block the formation of silicide and also block the source/drain implants, but since these structures 32 are not adjacent to gate polysilicon, the formation of these blocking nitride structures 32 requires an additional photolithography and etching step. Furthermore, the asymmetry between thicker nitride structure 32 on the drain side of gate 34 (i.e., adjacent to n+ region 28) and thinner nitride structure 32 on the source side, also requires the use of a silicide block pattern. In operation, as described in the Kunz et al. article, SCR 11 is triggered by either junction breakdown between n+ region 22 and p-substrate 10, or by punchthrough between n+ regions 22, 20 through p-substrate 10. As described in the Kunz et al. article, the voltage at which n+ region triggers the SCR action depends on strongly on the width of the channel between n+ regions 20, 22 that underlies nitride structure 32. However, this approach requires a photolithography operation to create structures 32 that block or mask the formation of silicide film 28 on the silicon surface. If this mask level is not otherwise available for other devices in the same integrated circuit, as it often is not, the additional cost for forming an ESD protection device according to FIG. 1f is significant.
While these approaches address the degraded bipolar gain caused by STI isolation structures, it is contemplated that other factors presented by advanced CMOS processes still limit the implementation of SCR-based structures in these technologies. As mentioned above, many advanced CMOS technologies utilize retrograde well doping profiles that limit the vertical conduction in ESD protection devices, and thus the parasitic bipolar transistor gain. In addition, many important integrated circuits are still required to have relatively high voltage swings at their input/output terminals, relative to the robustness of the manufacturing technology. In many of these high voltage I/O integrated circuits, the gate-coupled MOSFET has too low of a breakdown voltage (i.e., close to normal operating voltages) to permit their use in an ESD protection device.
By way of further background, the use of a compensated well in a vertical bipolar transistor is known, as described in copending application Ser. No. 09/977,025, filed Oct. 12, 2001, published as U.S. Patent Application Publication US/2002/0058373 A1 on May 16, 2002, commonly assigned herewith and incorporated herein by this reference.
By way of further background, the use of a counterdoped well in a drain-extended MOS transistor is known, as described in copending application Ser. No. 09/669,391, filed Sep. 26, 2000, commonly assigned herewith and incorporated herein by this reference.